The present invention relates to a modulation circuit of a digital-to-analog converter.
When conventional digital-to-analog conversion (D/A conversion) is executed, digital codes are converted to a pulse or a pulse train having a predetermined pulse width in a predetermined conversion period.
In FIG. 1, a digital circuit 1 outputs bit data D.sub.N -D.sub.1 each bit of which is generated from each of terminals D.sub.NT -D.sub.1T, and this bit data D.sub.N -D.sub.1 to be converted to analog data is input to a modulation circuit 3 of a digital-to-analog (D/A) converter 10. Each bit of digital data (digital codes) D is each output from the terminals D.sub.NT -D.sub.1T. For example, when N=5 (bits), D=D.sub.5 D.sub.4 D.sub.3 D.sub.2 D.sub.1. A binary counter 2 outputs signals Q.sub.N -Q.sub.1 for preparing timing signals for the D/A conversion, and the signals Q.sub.N -Q.sub.1 are input to the modulation circuit 3. A clock signal .phi. is inputted to the binary counter 2 to decide a minimum unit time of the D/A conversion. The modulation circuit 3 outputs an output voltage V.sub.P comprising a pulse or a pulse train having a predetermined pulse width as a whole in a predetermined conversion period in accordance with the bit data D.sub.N - D.sub.1 and the signals Q.sub.N -Q.sub.1. The level of the output voltage V.sub.P is converted to the level of an output voltage V.sub.L by a level conversion circuit 4 to finally obtain an output voltage V.sub.A as analog data having a proper voltage level through an integration circuit 5.
FIG. 2 shows a relationship between a clock signal .phi. and signals Q.sub.N -Q.sub.1 of the binary counter 2 when N=5 (bits). In this example, N is set to 5 for convenience in explaining the D/A conversion system of the present invention. When N=5 (bits), a conversion period T is 32t(=2.sup.5 t). (t: a minimum unit time for the D/A conversion)
Pulse width modulation (PWM) and pulse number modulation (PNM) are known as conventional methods for preparing the output voltage V.sub.P as shown in FIG. 3. Pulse width modulation enables the output voltage V.sub.P to output as a continuous pulse. Pulse number modulation enables output voltage V.sub.P to output as a combination of pulse trains with the minimum unit time t as a unit width. In pulse number modulation, though the pulse number of the output voltage V.sub.P increases between D=00001 and D-10000, the pulse number of the output voltage V.sub.P decreases between D=10001 and D=11111 because the waveform of the output voltage V.sub.P of D=00001-D32 01111 are superimposed on the waveform of the output V.sub.P of D=10000.
The high level period T.sub.P of the output voltage V.sub.P of the same digital data D within the conversion period T in the above methods occupies a same period, so that the value of analog data V.sub.A in the both methods is identical. The high level period T.sub.P is expressed as follows. EQU T.sub.P =t(2.sup.4 .times.D.sub.5 +2.sup.3 .times.D.sub.4 +2.sup.2 .times.D.sub.3 +2.sup.1 .times.D.sub.2 +2.sup.0 .times.D.sub.1)
Accordingly, in the both methods, the same digital data is converted as a pulse or a pulse train with an identical pulse width as a whole within the conversion period T.
However, the above methods have problems as follows. In the pulse width modulation, if a time constant of the integration circuit 5 is not large, a ripple is added to the waveform of the output voltage V.sub.A as analog data. Conversely, if the time constant is set large, a response against the bit data D.sub.N -D.sub.1 become improper.
In the pulse number modulation, on the contary, a time constant may be selected to be smaller than the time constant of the integration circuit 5 in the pulse width modulation except the maximum region and the minimum region of the digital data D. But, as shown in FIG. 4, an actual waveform (a) of the output voltage V.sub.P shows a rise time (tr) and a fall time (tf). When the level of the actual waveform (a) of the output voltage V.sub.P is converted by 50% of an amplitude, the level converted waveform (b) (the actual waveform (b) of the output voltage V.sub.L) is output. Width error (.DELTA.t) between the actual waveform (b) and a theoretical waveform (c) of the output voltage V.sub.L is inevitably produced and expensed as follows. ##EQU1## As this width error (.DELTA.t) becomes an error of one pulse, the width error of the digital data at D=10000 becomes a maximum as shown in FIG. 5. The width error (.DELTA.t) varies in accordance with the digital data value. If the value of the width error (.DELTA.t) shows an identical value, the width error can be compensated externally. On the contary, the width of the pulse width modulation shows as an identical value regardless of the digital data value.